Hardware authentication based on PUFs and SHA-3 2nd round candidates

Security features are getting a growing interest in microelectronics. Not only entities have to authenticate in the context of a high secure communication but also the hardware employed has to be trusted. Silicon Physical Unclonable Functions (PUFs) or Physical Random Functions, which exploits manufacturing process variations in integrated circuits, have been used to authenticate the hardware in which they are included and, based on them, several cryptographic protocols have been reported. This paper describes the hardware implementation of a symmetric-key authentication protocol in which a PUF is one of the relevant blocks. The second relevant block is a SHA-3 2nd round candidate, a Secure Hash Algorithm (in particular Keccak), which has been proposed to replace the SHA-2 functions that have been broken no long time ago. Implementation details are discussed in the case of Xilinx FPGAs.Junta de Andalucía P08-TIC-03674Comunidad Europea FP7-INFSO-ICT-248858Ministerio de Ciencia y Tecnología TEC2008-04920 y DPI2008-0384

FPGA implementation and DPA resistance analysis of a lightweight HMAC construction based on photon hash family

Lightweight security is currently a challenge in the field of cryptography. Most of applications designed for embedded scenarios often focus on authentication or on providing some form of anonymity and/or privacy. A well-known cryptographic element employed to provide such security is the HMAC construction. However, reported solutions are not suitable for constrained-resource scenarios due to their heavy approaches optimized for high-speed operations. In order to cover this lack, a lightweight implementation of HMAC based on the Photon family of hash functions is given in this work. Security of the construction against differential power attacks (DPA) is analyzed using a SASEBO-II development board. Implementation and performance results for Xilinx Virtex-5 FPGAs of the HMAC structure is provide

A Dual-Factor Access Control System Based on Device and User Intrinsic Identifiers

This paper proposes an access control system based on the simultaneous authentication of what the user has and who the user is. At enrollment phase, the wearable access device (a smart card, key fob, etc.) stores a template that results from the fusion of the intrinsic device identifier and the user biometric identifier. At verification phase, both the device and user identifiers are extracted and matched with the stored template. The device identifier is generated from the start-up values of the SRAM in the device hardware, which are exploited as a Physically Unclonable Function (PUF). Hence, if the device hardware is cloned, the authentic identifier is not generated. The user identifier is obtained from level-1 fingerprint features (directional image and singular points), which are extracted from the fingerprint images captured by the sensor in the access device. Hence, only genuine users with genuine devices are authorized to access and no sensitive information is stored or travels outside the access device. The proposal has been validated by using 560 fingerprints acquired in live by an optical sensor and 560 SRAM-based identifiers

A Fingerprint Retrieval Technique Using Fuzzy Logic-Based Rules

This paper proposes a global fingerprint feature named QFingerMap that provides fuzzy information about a fingerprint image. A fuzzy rule that combines information from several QFingerMaps is employed to register an individual in a database. Error and penetration rates of a fuzzy retrieval system based on those rules are similar to other systems reported in the literature that are also based on global features. However, the proposed system can be implemented in hardware platforms of very much lower computational resources, offering even lower processing time.Ministerio de Economía y Competitividad de Gobierno español y PO FEDER-FSE

Circuit authentication based on ring-oscillator PUFs

The use of Ring Oscillator PUFs to provide circuit authentication is analyzed in this paper. The limitations of the previously reported approach in terms of false rejection (due to high intra-die variations) and false acceptance (due to small inter-die variations) are discussed. These limitations are overcome by a new proposal that does not increase considerably hardware complexity and, besides, provides lower power consumption and/or higher speed to achieve high security requirements. All these issues are illustrated with experimental results obtained with FPGAs from Xilin

Automatic extraction of linguistic models for image description

This paper describes a methodology to extract fuzzy models that describe linguistically the low-level features of an image (such as color, texture, etc.). The methodology combines grid-based algorithms with clustering and tabular simplification methods to compress image information into a small number of fuzzy rules with high linguistic meaning. All the steps of the methodology are carried out with the help offered by the tools of Xfuzzy 3 environment, so we can define, simplify, tune and verify the fuzzy models automatically. Several examples are included to illustrate the advantages of the methodolog

A digital circuit for extracting singular points from fingerprint images

Since singular point extraction plays an important role in many fingerprint recognition systems, a digital circuit to implement such processing is presented herein. A novel algorithm that combines hardware efficiency with precision in the extraction of the points has been developed. The circuit architecture contains three main building blocks to carry out the three main stages of the algorithm: extraction of a partitioned directional image, smoothing, and searching for the patterns associated with singular points. The circuit processes the pixels in a serial way, following a pipeline scheme and executing in parallel several operations. The design flow employed has been supported by CAD tools. It starts with high-level descriptions and ends with the hardware prototyping into a FPGA from Xilinx

Model-based design for selecting fingerprint recognition algorithms for embedded systems

Most of contributions for biometric recognition solutions (and specifically for fingerprint recognition) are implemented in software on PC or similar platforms. However, the wide spread of embedded systems means that fingerprint embedded systems will be progressively demanded and, hence, hardware dedicated solutions are needed to satisfy their constraints. CAD tools from Matlab-Simulink ease hardware design for embedded systems because automatize the design process from high-level descriptions to device implementation. Verification of results is set at different abstraction levels (high- level description, hardware code simulation, and device implementation). This paper shows how a design flow based on models facilitates the selection of algorithms for fingerprint embedded systems. In particular, the search of a solution for directional image extraction suitable for its application to singular point extraction is detailed. Implementation results in terms of area occupation and timing are presented for different Xilinx FPGAs.Ministerio de Economía y Competitividad TEC2011-24319Junta de Andalucía P08-TIC-03674Comunidad Europea FP7-INFSO-ICT-24885

High-Speed and Low-Cost Implementation of Explicit Model Predictive Controllers

This paper presents a new form of piecewise-affine (PWA) solution, referred to as PWA hierarchical (PWAH), to approximate the explicit model predictive control (MPC) law, achieving a very rapid control response with the use of very few computational and memory resources. This is possible because PWAH controllers consist of single-input single-output PWA modules connected in cascade so that the parameters needed to define them increase linearly instead of exponentially with the input dimension of the control problem. PWAH controllers are not universal approximators but several explicit MPC controllers can be efficiently approximated by them. A methodology to design PWAH controllers is presented and validated with application examples already solved by MPC approaches. The designed PWAH controllers implemented in field-programmable gate arrays provide the highest control speed using the fewest resources compared with the other digital implementations reported in the literature.Ministerio de Economía, Industria y Competitividad TEC2014-57971-